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? semiconductor components industries, llc, 2012 june, 2012 ? rev. p0 1 publication order number: ncp81044/d ncp81044 product preview low voltage synchronous buck controller the ncp81044 is a pwm controller designed to operate from a 5 v or 12 v supply. these devices are capable of producing an output voltage as low as 0.8 v. these 8 ? pin devices provide an optimal level of integration to reduce size and cost of the power supply. the ncp81044 provides a 1 a gate driver design and an internally set 275 khz oscillator. in addition to the 1 a gate drive capability, other efficiency enhancing features of the gate driver include adaptive non ? overlap circuitry. the devices also incorporate an externally compensated error amplifier and a capacitor programmable soft ? start function. protection features include programmable short circuit protection and under voltage lockout (uvlo). the ncp81044 comes in an 8 ? pin soic package. features ? input voltage range from 4.5 to 13.2 v ? 275 khz internal oscillator ? boost pin operates to 30 v ? voltage mode pwm control ? 0.8 v 1.0 % internal reference voltage ? adjustable output voltage ? capacitor programmable soft ? start ? internal 1 a gate drivers ? 80% max duty cycle ? input under voltage lockout ? programmable current limit ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? graphics cards ? desktop computers ? servers / networking ? dsp & fpga power supply ? dc ? dc regulator modules this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. soic ? 8 d suffix case 751 1 8 marking diagram pin connections 81044 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free device 1 bst 8 phase 2 tg 3 gnd 4 bg 7 comp/dis 6 fb 5 v cc (top view) 81044 alyw device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 1 8 http://onsemi.com NCP81044DR2G soic ? 8 (pb ? free) 2500/tape & reel
ncp81044 http://onsemi.com 2 figure 1. typical application diagram bst tg gnd bg comp/dis fb v cc v out phase 12 v 3.3 v figure 2. detailed block diagram latch fb comp/dis 0.8 v (v ref ) v cc + - clock ramp osc osc r s q pwm out fault + - 2 v + - fault tg bst phase v cc bg gnd 7 1 2 8 4 3 fault + - scp por uvlo 5 + - 6 vocth gm r set
ncp81044 http://onsemi.com 3 pin function description pin no. symbol description 1 bst supply rail for the floating top gate driver. to form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to bst pin). connect a capacitor (c bst ) between this pin and the phase pin. typical values for c bst range from 0.1 f to 1 f. ensure that c bst is placed near the ic. 2 tg top gate mosfet driver pin. connect this pin to the gate of the top n ? channel mosfet. 3 gnd ic ground reference. all control circuits are referenced to this pin. 4 bg bottom gate mosfet driver pin. connect this pin to the gate of the bottom n ? channel mosfet. 5 v cc supply rail for the internal circuitry. operating supply range is 4.5 v to 13.2 v. decouple with a 1 f capacitor to gnd. ensure that this decoupling capacitor is placed near the ic. 6 fb this pin is the inverting input to the error amplifier. use this pin in conjunction with the comp pin to compensate the voltage ? control feedback loop. connect this pin to the output resistor divider (if used) or dir- ectly to v out . 7 comp/dis compensation pin. this is the output of the error amplifier (ea) and the non ? inverting input of the pwm com- parator. use this pin in conjunction with the fb pin to compensate the voltage ? control feedback loop. the com- pensation capacitor also acts as a soft ? start capacitor. pull this pin low for disable. 8 phase switch node pin. this is the reference for the floating top gate driver. connect this pin to the source of the top mosfet. absolute maximum ratings pin name symbol v max v min main supply voltage input v cc 15 v ? 0.3 v bootstrap supply voltage input bst 35 v wrt/pgnd 40 v < 50 ns wrt/pgnd 15 v wrt/sw ? 0.3 v ? 0.3 v ? 0.3 v switching node (bootstrap supply return) phase 35 v 40 v < 50 ns ? 5.0 v ? 10 v for < 200 ns high ? side driver output (top gate) tg 30 v wrt/gnd 15 v wrt/phase ? 0.3 v wrt/phase ? 2 v < 200 ns wrt/phase low ? side driver output (bottom gate) bg 15 v ? 0.3 v ? 5.0 v for < 200 ns feedback fb 5.5 v ? 0.3 v comp/disable comp/dis 5.5 v ? 0.3 v maximum ratings rating symbol value unit thermal resistance, junction ? to ? ambient r ja 165 c/w thermal resistance, junction ? to ? case r jc 45 c/w operating junction temperature range t j 0 to 125 c operating ambient temperature range t a 0 to 70 c storage temperature range t stg ? 55 to +150 c lead temperature soldering (10 sec): reflow (smd styles only) pb ? free 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
ncp81044 http://onsemi.com 4 electrical characteristics (0 c < t a < 70 c; 4.5 v < v cc < 13.2 v, 4.5 v < [bst ? phase] < 13.2 v, 4.5 v < bst < 30 v, 0 v < phase < 21 v, c tg = c bg = 1.0 nf, for min/max values unless otherwise noted.) characteristic conditions min typ max unit input voltage range ? 4.5 ? 13.2 v boost voltage range ? 4.5 ? 26.5 v supply current quiescent supply current v fb = 1.0 v, no switching, v cc = 13.2 v 1.0 ? 8.0 ma boost quiescent current v fb = 1.0 v, no switching, v cc = 13.2 v 0.1 ? 1.0 ma under voltage lockout uvlo threshold v cc rising edge 3.8 ? 4.2 v uvlo hysteresis ? ? 350 ? mv switching regulator vfb feedback voltage, control loop in regulation t a = 0 to 70 c 792 800 808 mv oscillator frequency t a = 0 to 70 c 250 275 300 khz ramp ? amplitude voltage 0.8 1.1 1.4 v minimum duty cycle 0 ? ? % maximum duty cycle 80 88 93 % error amplifier (gm) transconductance 3.0 ? 4.4 mmho open loop dc gain 55 70 ? db output source current output sink current v fb < 0.8 v v fb > 0.8 v 80 80 120 120 ? ? a input bias current ? 0.1 1.0 a soft ? start ss source current v fb < 0.8 v 8.49 11 13.3 a switch over threshold v fb = 0.8 v ? 100 ? % of vref gate drivers upper gate source v cc = 12 v, vtg = vbg = 2.0 v ? 1.0 ? a upper gate sink ? 1.0 ? a lower gate source ? 1.0 ? a lower gate sink ? 2.0 ? a tg falling to bg rising delay v cc = 12 v, tg < 2.0 v, bg > 2.0 v ? 40 90 ns bg falling to tg rising delay v cc = 12 v, bg < 2.0 v, tg > 2.0 v ? 35 90 ns enable threshold 0.3 0.4 0.5 v over ? current protection ocset current source sourced from bg pin, before ss 8.9 10 11.1 a oc switch ? over threshold ? 700 ? mv fixed oc threshold ? ? 375 ? mv
ncp81044 http://onsemi.com 5 typical characteristics (t a = 25 c unless otherwise noted) figure 3. i cc vs. temperature figure 4. oscillator frequency (f sw ) vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 70 60 50 40 30 20 10 0 3.5 3.8 4.1 4.4 4.7 5.0 70 60 50 40 30 20 10 0 198 199 200 201 202 203 figure 5. soft start sourcing current vs. temperature figure 6. scp threshold vs. temperature t j , junction temperature ( c) t j , junction temperature ( c) 70 60 50 40 30 20 10 0 8 9 10 11 12 13 14 70 60 50 40 30 20 10 0 325 335 345 355 365 375 figure 7. reference voltage (v ref ) vs. temperature t j , junction temperature ( c) 70 60 50 40 30 20 10 0 792 794 796 800 802 804 806 808 i cc (ma) f sw , frequency (khz) soft start sourcing current ( a) scp threshold (mv) v ref , reference (mv) v cc = 5 v v cc = 12 v 798
ncp81044 http://onsemi.com 6 detailed operating description general the ncp81044 is a pwm controller intended for dc ? dc conversion from 5.0 v & 12 v buses. the devices have a 1 a internal gate driver circuit designed to drive n ? channel mosfets in a synchronous ? rectifier buck topology. the output voltage of the converter can be precisely regulated down to 800 mv 1.0% when the v fb pin is tied to v out . the switching frequency, is internally set to 275 khz. a high gain operational transconductance error amplifier (ota) is used. duty cycle and maximum pulse width limits in steady state dc operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. the devices can achieve an 80% duty cycle. there is a built in off ? time which ensures that the bootstrap supply is charged every cycle. this part can allow a 12 v to 0.8 v conversion at 275 khz. input voltage range (v cc and bst) the input voltage range for both v cc and bst is 4.5 v to 13.2 v with respect to gnd and phase, respectively. although bst is rated at 13.2 v with respect to phase, it can also tolerate 26.4 v with respect to gnd. external enable/disable when the comp pin voltage falls or is pulled externally below the 400 mv threshold, it disables the pwm logic and the gate drive outputs. in this disabled mode, the operational transconductance amplifier (eota) output source current is reduced and limited to the soft ? start mode of 10 a. normal shutdown behavior normal shutdown occurs when the ic stops switching because the input supply reaches uvlo threshold. in this case, switching stops, the internal ss is discharged, and all gate pins go low. the switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. external soft ? start the ncp81044 features an external soft ? start function, which reduces inrush current and overshoot of the output voltage. soft ? start is achieved by using the internal current source of 10 a (typ), which charges the external integrator capacitor of the transconductance amplifier. figure 8 is a typical soft ? start sequence. this sequence begins once v cc surpasses its uvlo threshold and ocp programming is complete. during soft ? start, as the comp pin rises through 400 mv, the pwm logic and gate drives are enabled. when the feedback voltage crosses 800 mv, the eota will be given contr ol to switch to its higher regulation mode output current of 120 a. figure 8. soft ? start implementation 4.2 v 0.9 v 0.8 v comp v cc v fb bg tg v out normal ss por uvlo 550 mv 50 mv ocp program ming
ncp81044 http://onsemi.com 7 uvlo undervoltage lockout (uvlo) is provided to ensure that unexpected behavior does not occur when v cc is too low to support the internal rails and power the converter. for the ncp81044, the uvlo is set to permit operation when converting from a 5.0 input voltage. overcurrent threshold setting ncp81044 can easily program an overcurrent threshold ranging from 50 mv to 550 mv, simply by adding a resistor (rset) between bg and gnd. during a short period of time following v cc rising over uvlo threshold, an internal 10 a current (i ocset ) is sourced from bg pin, determining a voltage drop across r ocset . this voltage drop will be sampled and internally held by the device as overcurrent threshold. the oc setting procedure overall time length is about 6 ms. connecting a r ocset resistor between bg and gnd, the programmed threshold will be: i octh i ocset r ocset r ds(on) (eq. 1) rset values range from 5 k to 55 k . in case r ocset is not connected, the device switches the ocp threshold to a fixed 375 mv value: an internal safety clamp on bg is triggered as soon as bg voltage reaches 700 mv, enabling the 375 mv fixed threshold and ending oc setting phase. the current trip threshold tolerance is 25 mv. the accuracy of the set point is best at the highest set point (550 mv). the accuracy will decrease as the set point decreases. current limit protection in case of a short circuit or overload, the low ? side (ls) fet will conduct large currents. the controller will shut down the regulator in this situation for protection against overcurrent. the low ? side r ds(on) sense is implemented at the end of each of the ls ? fet turn ? on duration to sense the over current trip point. while the ls driver is on, the phase voltage is compared to the internally generated ocp trip voltage. if the phase voltage is lower than ocp trip voltage, an overcurrent condition occurs and a counter is initiated. when the counter completes, the pwm logic and both hs ? fet and ls ? fet are turned off. the controller has to go through a power on reset (por) cycle to reset the ocp fault. drivers the ncp81044 includes gate drivers to switch external n ? channel mosfets. this allows the devices to address high ? power as well as low ? power conversion requirements. the gate drivers also include adaptive non ? overlap circuitry. the non ? overlap circuitry increase efficiency, which minimizes power dissipation, by minimizing the body diode conduction time. a detailed block diagram of the non ? overlap and gate drive circuitry used in the chip is shown in figure 9. figure 9. block diagram bst tg phase bg gnd r set fault fault 8 2 1 4 3 v cc 2 v - + - + careful selection and layout of external components is required, to realize the full benefit of the onboard drivers. the capacitors between v cc and gnd and between bst and swn must be placed as close as possible to the ic. the current paths for the tg and bg connections must be optimized. a ground plane should be placed on the closest layer for return currents to gnd in order to reduce loop area and inductance in the gate drive circuit.
ncp81044 http://onsemi.com 8 application section input capacitor selection the input capacitor has to sustain the ripple current produced during the on time of the upper mosfet, so it must have a low esr to minimize the losses. the rms value of this ripple is: iin rms i out d (1 d) , where d is the duty cycle, iin rms is the input rms current, & i out is the load current. the equation reaches its maximum value with d = 0.5. loss in the input capacitors can be calculated with the following equation: p cin esr cin iin rms 2 , where p cin is the power loss in the input capacitors & esr cin is the effective series resistance of the input capacitance. due to large di/dt through the input capacitors, electrolytic or ceramics should be used. if a tantalum must be used, it must by surge protected. otherwise, capacitor failure could occur. calculating input start-up current to calculate the input start up current, the following equation can be used. i inrush c out v out t ss , where i inrush is the input current during start-up, c out is the total output capacitance, v out is the desired output voltage, and t ss is the soft start interval. if the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used. calculating soft start time to calculate the soft start time, the following equation can be used. t ss (c p c c )* v i ss where c c is the compensation as well as the soft start capacitor, c p is the additional capacitor that forms the second pole. i ss is the soft start current v is the comp voltage from 0.9 v to until it reaches regulation: ((d * ramp) + 0.9) output capacitor selection the output capacitor is a basic component for the fast response of the power supply. in fact, during load transient, for the first few microseconds it supplies the current to the load. the controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. during a load step transient the output voltage initial drops due to the current variation inside the capacitor and the esr. ((neglecting the effect of the effective series inductance (esl)): v out ? esr i out esr cout where v out-esr is the voltage deviation of v out due to the effects of esr and the esr cout is the total effective series resistance of the output capacitors. a minimum capacitor value is required to sustain the current during the load transient without discharging it. the voltage drop due to output capacitor discharge is given by the following equation: v out ? discharge i out 2 l out 2 c out (v in d v out ) , where v out-discharge is the voltage deviation of v out due to the effects of discharge, l out is the output inductor value & v in is the input voltage. it should be noted that v out-discharge and v out-esr are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the esl). inductor selection both mechanical and electrical considerations influence the selection of an output inductor. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space-constrained applications. from an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by: slewrate lout v in v out l out this equation implies that larger inductor values limit the regulator?s ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. this results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. the peak-to-peak ripple current for ncp81044 is given by the following equation: ipk pk lout v out (1 d) l out 275 khz , where ipk-pk lout is the peak to peak current of the output. from this equation it is clear that the ripple current increases as l out decreases, emphasizing the trade-off between dynamic response and ripple current.
ncp81044 http://onsemi.com 9 feedback and compensation the ncp81044 allows the output of the dc-dc converter to be adjusted from 0.8 v to 5.0 v via an external resistor divider network. the controller will try to maintain 0.8 v at the feedback pin. thus, if a resistor divider circuit was placed across the feedback pin to v out , the controller will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 v at the fb pin. fb r1 r2 v out the relationship between the resistor divider network above and the output voltage is shown in the following equation: r 2 r 1 v ref v out v ref resistor r1 is selected based on a design tradeoff between efficiency and output voltage accuracy. for high values of r1 there is less current consumption in the feedback network, however the trade off is output voltage accuracy due to the bias current in the error amplifier. the output voltage error of this bias current can be estimated using the following equation (neglecting resistor tolerance): error% 0.1 a r 1 v ref 100% once r1 has been determined, r2 can be calculated. gm ea figure 10. type ii transconductance error amplifier r 1 r 2 v ref + ? c p c c r c figure 10 shows a typical t ype ii transconductance error amplifier (eota). the compensation network consists of the internal error amplifier and the impedance networks zin (r 1 , r 2 ) and external z fb (r c , c c and c p ). the compensation network has to provide a closed loop transfer function with the highest 0 db crossing frequency to have fast response (but always lower than f sw /8) and the highest gain in dc conditions to minimize the load regulation. a stable control loop has a gain crossing with -20 db/decade slope and a phase margin greater than 45 . include worst-case component variations when determining phase margin. loop stability is defined by the compensation network around the eota, the output capacitor, output inductor and the output divider. figure 11 shows the open loop and closed loop gain plots. compensation network frequency: the inductor and capacitor form a double pole at the frequency f lc 1 2 l o c o the esr of the output capacitor creates a ?zero? at the frequency, f esr 1 2 esr c o the zero of the compensation network is formed as, f z 1 2 r c c c the pole of the compensation network is calculated as, f p 1 2 r c c p figure 11. gain plot of the error amplifier thermal considerations the power dissipation of the ncp81044 varies with the mosfets used, v cc , and the boost voltage (v bst ). the average mosfet gate current typically dominates the control ic power dissipation. the ic power dissipation is determined by the formula: p ic (i cc v cc ) p tg p bg where: p ic = control ic power dissipation, i cc = ic measured supply current, v cc = ic supply voltage, p tg = top gate driver losses, p bg = bottom gate driver losses. the upper (switching) mosfet gate driver losses are: p tg q tg f sw v bst where: q tg = total upper mosfet gate charge at vbst, f sw = the switching frequency, v bst = the bst pin voltage.
ncp81044 http://onsemi.com 10 the lower (synchronous) mosfet gate driver losses are: p bg q bg f sw v cc where: q bg = total lower mosfet gate charge at v cc . the junction temperature of the control ic can then be calculated as: t j t a p ic ja where: t j = the junction temperature of the ic, t a = the ambient temperature, ja = the junction ? to ? ambient thermal resistance of the ic package. the package thermal resistance can be obtained from the specifications section of this data sheet and a calculation can be made to determine the ic junction temperature. however, it should be noted that the physical layout of the board, the proximity of other heat sources such as mosfets and inductors, and the amount of metal connected to the ic, impact the temperature of the device. use these calculations as a guide, but measurements should be taken in the actual application. layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. the figure below shows the critical power components of the converter. to minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in the figure below should be located as close together as possible. please note that the capacitors c in and c out each represent numerous physical capacitors. it is desirable to locate the ncp81044 within 1 inch of the mosfets, q1 and q2. the circuit traces for the mosfets? gate and source connections from the ncp81044 must be sized to handle up to 2 a peak current. figure 12. components to be considered for layout specifications design example i: type ii compensation (electrolytic cap. with large esr) switching frequency f sw = 275 khz output capacitance r esr = 45 m /each output capacitance c out = 2 1800 f output inductance l out = 1 h input voltage v in = 12 v output voltage v out = 1.6 v choose the loop gain crossover frequency; f co 1 5 f sw 55 khz the corner fr equency of the output filter is calculated below; f lc 1 2 1 h 3600 f 2.65 khz check that the esr zero frequency is not too high; f esr 1 2 r esr c o
f co 10 f esr 1 2 45 m 2 (1800 f 2) 2khz if esr zero is larger than f co /10, type iii compensation is necessary. choose c c for the crossover frequency and the soft start c c 100 nf the compensation capacitor (c c ) is related to the loop gain magnitude, zero position and the soft start. by adjusting the value of this compensation capacitor, the crossover frequency and the soft start time can be adjusted. zero of the compensation network is calculated as follows; f z f lc 2.65 khz r c 1 2 f z c c 1 2 2.65 khz 100 nf 600.6 pole of the compensation network is calculated as follows; f p f sw 275 khz c p 1 2 f p r c 1 2 275 khz 600.6 963.6 pf the recommended compensation values are; r c = 604, c c = 100 nf, c p = 1000 pf
ncp81044 http://onsemi.com 11 blue curve: gain-frequency red curve: gain-frequency (phase margin = 61.417 degree, gain margin = 9.347 db) figure 13. closed-loop voltage loop-gain of the ncp81044 design example ii: type iii compensation (oscon cap. with small esr; do not place r c , c c , c p ) switching frequency f sw = 275 khz output capacitance r esr = 7 m /each output capacitance c out = 2 560 f output inductance l out = 1 h input voltage v in = 12 v output voltage v out = 1.6 v choose the loop gain crossover frequency; f co 1 5 f sw 55 khz the corner fr equency of the output filter is calculated below; f lc 1 2 1 h 1120 f 4.7 khz check the esr zero frequency; f esr 1 2 r esr c o f esr 1 2 7m 560 f 40.6 khz choose c c1 for the soft start c c1 33 nf the compensation capacitor (c c1 ) is related to the loop gain magnitude, one zero position and the soft start. by adjusting the value of this compensation capacitor, the crossover frequency and the soft start time can be adjusted. zeros of the compensation network are calculated as follows; 1st zero; f z1 f lc 10 470 hz r c1 1 2 f z1 c c1 1 2 470 hz 30 nf 11.3 k r c1 should be much larger than 2/gm in order to get the stable system with transconductance amplifier. choose r c1 = 12.1 k 2nd zero; choose r3 for the crossover frequency. r3 should be much larger than 2/gm for the stable system. r3 10 k f z2 f lc 4.7 khz c20 1 2 f z2 r3 1 2 4.7 khz 10 k 3.4 nf choose c20 = 3.3 nf poles of the compensation network are calculated as follows; 1st pole; choose r4 to cancel the output capacitor esr zero. f p1 f esr 40.6 khz r4 1 2 f p1 c20 1 2 40.6 khz 3.3 n 1.2 k
ncp81044 http://onsemi.com 12 after choose r4 value, adjust r4 to get enough phase margin r4 = 665 2nd pole; choose c p1 to eliminate the noise; f p2 f sw 275 khz c p1 1 2 f p2 r c1 1 2 275 khz 12 k 48.23 pf choose c p1 = 47 pf the recommended compensation values are; r2 = 10 k , r3 = 10 k , r4 = 665 , r c1 = 12.1 k , c c1 = 33 nf, c p1 = 47 pf, c20 = 3.3 nf blue curve: gain-frequency red curve: gain-frequency (phase margin = 80.285 degree, gain margin = 19.362 db) figure 14. closed-loop voltage loop-gain of the ncp81044
ncp81044 http://onsemi.com 13 figure 15. demo board pcb layout vin v bst gnd outp u tg bg switch_node vcc gnd note : g ating length s note : g ating length sho gnd comp fb gnd so8 ? fl ipak dpak ipak so8 ? fl dpak ipak so8 ? fl dpak ipak so8 ? fl dpak dual placement site dual placement site dual placement site dual placement site dual placement site dual placement site 1 switch_node tg vout bst bg vin comp vbst vcc fb gnd vout q12 dnp d g s c9 1uf c22 10uf tp111 c20 dnp + c4 1500uf c19 10uf tp112 tp97 rc1 dnp r5 5.11 r8 dnp rc 604 r7 0 tp7 c23 10uf r4 dnp q4 ntd4815 c8 1uf u1 ncp81044 1 7 6 4 8 3 2 5 bst comp fbbg phase gnd tg vcc tp98 r6 0 + c12 1800uf cp1 dnp tp109 r639 0 q11 dnp d g s tp9 + c24 dnp c11 0.1uf cp 100pf q7 ntd4806 mh1 tp110 tp105 + c13 1800uf q2 ntd4815 c25 10uf tp95 q3 ntd4815 + c5 dnp tp106 tp100 q8 ntd4806 c16 10uf q9 dnp d g s tp94 c21 dnp tp104 cc1 dnp cc 0.1uf q5 ntd4806 tp107 tp1 r90 mh4 tp102 tp93 tp113 q6 ntd4806 q1 ntd4815 tp96 tp108 tp103 tp20 l11uh mh3 c17 10uf tp2 + c15 dnp r3 1.02k tp99 c18 10uf r1 10 cr1 bas1 16lt1 1 3 mh2 q10 dnp d g s r2 1.02k l2dnp tp101
ncp81044 http://onsemi.com 14 bill of materials item number part reference value quantity mfg 1 c4 1500 f 1 panasonic 2 c5 dnp 1 - 3 c8,c9 1 f 2 taiyo yuden 4 c11 0.1 f 1 avx 5 c12,c13 1800 f 2 panasonic 6 c15,c24 dnp 2 - 7 c16,c17,c18,c19,c22,c23,c25 10 f 7 panasonic 8 c20,cc1,cp1 dnp 3 - 9 c21 dnp 1 - 10 cc 0.1 f 1 tdk 11 cr1 bas116lt1 1 on semiconductor 12 cp 100 pf 1 panasonic 13 j9 20pin 2row 1 molex 14 j23 5pin 1 pasternack enterprises 15 l1 1 h 1 panasonic 16 l2 dnp 1 - 17 q1,q2 ntd4815 2 on semiconductor 18 q3,q4 ntd4815 2 on semiconductor 19 q5,q6 ntd4806 2 on semiconductor 20 q7,q8 ntd4806 2 on semiconductor 21 q9,q10,q11,q12 dnp 4 - 22 q17,q18,q19,q20,q21,q22,q23,q24,q25,q26, q27,q28,q29,q30,q31,q32,q33,q34,q35,q36, q37,q38,q39,q40 nths5404t1 24 on semiconductor 23 r1 10 1 panasonic 24 r2,r3 1.02 k 2 dale 25 r4,rc1 dnp 2 - 26 r5 5.11 1 dale 27 r6,r7,r639 0 3 panasonic 28 r8 dnp 1 - 29 r9 0 1 dale 30 r551,r552,r553,r569,r570,r571,r584,r585, r586,r599,r600,r601,r608,r609,r610,r617, r618,r619,r626,r627,r628,r635,r636,r637 100 k 24 dale 31 r602,r603,r604,r605,r606,r607,r611,r612, r613,r614,r615,r616,r620,r621,r622,r623, r624,r625,r629,r630,r631,r632,r633,r634 0.56 24 panasonic 32 r638 49.9 1 dale 33 rc 604 1 dale 34 tp97,tp98,tp99,tp100,tp101,tp102,tp103, tp104,tp105,tp106,tp107,tp108,tp109, tp110,tp111,tp112 tp 16 keystone 35 u1 ncp81044 1 on semiconductor
ncp81044 http://onsemi.com 15 figure 16. gate waveforms 20 a load sustaining figure 17. over current protection (12.4 a dc trip) figure 18. start-up sequence figure 19. transient response 0-10 a load step efficiency 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 0246810121416 load current (a) efficiency (%) figure 20. efficiency vs. load current
ncp81044 http://onsemi.com 16 package dimensions soic ? 8 d suffix case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp81044/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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